In the field of semiconductor device manufacturing, active semiconductor devices such as, for example, transistors are manufactured through processes commonly known as front end of line (FEOL) technology. Such transistors may include, inter alia, a field-effect-transistor (FET) which may be more specifically, as one un-limiting example, a complementary metal-oxide-semiconductor FET or CMOS-FET. Moreover, a FET may be a p-type dopant doped FET (pFET) or an n-type dopant doped FET (nFET). Different types of transistors may be manufactured on a common semiconductor substrate or semiconductor chip.
It is known in the art that performance of semiconductor transistors, including those described above, may be greatly improved through means of enhancing mobility of electrons or holes, depending on the type of the transistors, in the channel region of the transistors. For example, it is known in the art that uniaxial tensile stress may enhance electron mobility in certain types of doped silicon (Si) and therefore may be used to improve or enhance drive current of an nFET transistor. In order to achieve uniaxial tensile stress in the channel region of an nFET transistor, one common approach is through the formation of a silicon-carbon (Si:C) film or Si:C layer, in the form of stressors, in the source/drain regions of the nFET transistor. In other words, the approach forms embedded Si:C stressors in the source/drain regions of the nFET transistor. This is an approach similar to a complementary process of applying embedded silicon-germanium (e-SiGe) source/drain to improve performance of a pFET transistor over the years.
There are two well known approaches to achieve or to form Si:C source/drain stressors: one is through chemical vapor deposition (CVD) of cyclic epitaxial Si:C layers and the other is through solid phase epitaxy (SPE) after a self amorphizing carbon (C) implantation or, in other words, through amorphizing C implantation which is followed by a thermal annealing step to cause re-crystallization of silicon. However, both approaches have their respective drawbacks. For example, unlike e-SiGe deposition that is used in enhancing pFET transistor performance, in order to achieve robust selectivity relative to surrounding isolating/insulating materials such as nitride, oxide, and/or oxynitride, such that to form Si:C epitaxial film only in designated source/drain regions of the nFET transistor with highly substitutional carbon level (for example, more than 1.5% carbon in atomic concentration) in the formed Si:C film, a low temperature and cyclic CVD deposition process is required. The deposition needs to be carried out at the relatively low temperature (below or near 600 C) because carbon is highly unstable in Si lattice, and the cyclic deposition is required due to the low solid solubility of carbon. As a result, the CVD deposition process generally has a low growth rate and thus low throughput. Furthermore, achieving facetless epitaxial growth, which is important in forming low-resistant contact, under these conditions is often found difficult.
On the other hand, Si:C formation by amorphizing C implantation followed by a SPE process has a couple of drawbacks as well. For example, in order to achieve maximum stress benefit, Si:C layer should be formed at some certain depth (e.g. around 30 to 40 nm) below the channel level of the nFET transistor. However, with C being a low mass atom the implantation may create a significant implant tail, hence the gate height will limit the maximum C implant energy in order not to cause gate punch-through, which in-turn limits the depth of Si:C layer achievable. This may become a serious issue for short channel devices and cause defective re-crystallization in embedded source-drain region. Even though one may be able to approximate the Si:C layer by using several different C implants with different energy levels, it becomes very difficult to achieve true box-shape like Si:C profile, which is generally desirable for achieving optimum stress effect.